01-Introduction

02-Continuous-Time signal

03-Discrete-Time Signal

04-Signal Representation

05-Unit Sample Sequence

06-Unit Step Sequence

07-Analog-to-Digital conversion

08-Digital-to-Analog

09-Quantization Error SRN, SINAD-Part1

09-Quantization Error SRN, SINAD-Part2

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Section 1 01-Introduction to Digital Filter

02-FIR general architecture

03-Mobile Average Filter-lecture

03-Mobile Average Filter-sim

04-Frequency response

04-Frequency response-example

05-Impulse response

05-Impulse response-example

06-Step Response

06-Step Response-example

Section 2 material Download

Section 2 01-Introduction to Fixed point arithmetic

02-Floating point - Fixed Point

03-Fixed point representation

04-Adder-Lecture

04-Adder-VHDL Simulation

05-Subtraction-Lecture

06-Multiplier-Lecture part 1

06-Multiplier-Lecture part2

06-Multiplier-VHDL simulation

VHDL Exercise Download

Section 3 Coming Soon

Sectrion 4 - Coming Soon

01-VHDL implementation of Mobile Average Filter-Lecture

01-VHDL implementation of Mobile Average Filter-VHDL simulation (plain implementation)

01-VHDL implementation of Mobile Average Filter-VHDL Simulation (FIR like)

01-VHDL implementation of Mobile Average Filter-VHDL (optimized implementation)

02-VHDL implementation of a classic FIR-Lecture

02-VHDL implementation of a classic FIR-VHDL Simulation

03-VHDL implementation of a symmetric FIR-Lecture

03-VHDL implementation of a symmetric FIR-VHDL simulation

04-VHDL implementation of a antisymmetric FIR-Lecture

04-VHDL implementation of a antisymmetric FIR-VHDL simulation

05-VHDL implementation of a CNN Kernel-Lecture

05-VHDL implementation of a CNN Kernel-VHDL simulation

Section 5 Section 6 - Coming Soon

Section BONUS - Coming Soon

<p>Learn How to Implement High Speed Digital Signal Processing in FPGA using VHDL</p>

Mastering DSP in VHDL

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Mastering DSP in VHDL

SURF VHDL

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